Browsing by Author Bhat, K.G.
Showing results 1 to 4 of 4
| Issue Date | Title | Author(s) | Supervisor(s) |
| 2012 | A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC | Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, M.S. | - |
| 2016 | An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC | Bhat, K.G.; Laxminidhi, T.; Bhat, M.S. | - |
| 2019 | A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture | Bhat, K.G.; Laxminidhi, T.; Bhat, M.S. | - |
| 2019 | A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture | Bhat, K.G.; Laxminidhi, T.; Bhat, M.S. | - |
