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Browsing by Author Talawar, B.
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Showing results 1 to 20 of 27
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Issue Date
Title
Author(s)
Supervisor(s)
2018
Accurate Performance Analysis of 3D Mesh Network on Chip Architectures
Halavar, B.
;
Talawar, B.
-
2018
Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)
Pasupulety, U.
;
Halavar, B.
;
Talawar, B.
-
2019
Accurate Router Level Estimation of Network-on-Chip Architectures using Learning Algorithms
Kumar, A.
;
Talawar, B.
-
2019
Analysis of cache behaviour and software optimizations for faster on-chip network simulations
Prasad, B.M.P.
;
Parane, K.
;
Talawar, B.
-
2016
Analysis of ring topology for NoC architecture
Kamath, A.
;
Saxena, G.
;
Talawar, B.
-
2016
Cache analysis and software optimizations for faster on-chip network simulations
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
2015
A Crossbar Interconnection Network in DNA
Talawar, B.
-
2019
Design of an adaptive and reliable network on chip router architecture using FPGA
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
2019
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures
Halavar, B.
;
Pasupulety, U.
;
Talawar, B.
-
2018
Floorplan based performance evaluation of 3d variants of mesh and BFT networks-on-chip
Halavar, B.
;
Talawar, B.
-
2018
FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
2017
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images
Upadhya, A.H.K.
;
Talawar, B.
;
Rajan, J.
-
2019
High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks
Prabhu, Prasad, B.M.
;
Parane, K.
;
Talawar, B.
-
2019
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs
Prabhu, P.B.M.
;
Parane, K.
;
Talawar, B.
-
2020
LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
2018
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks
Kumar, A.
;
Talawar, B.
-
2019
MMAS on GPU for Large TSP Instances
Yelmewad, P.
;
Kumar, A.
;
Talawar, B.
-
2018
Near Optimal Solution for Traveling Salesman Problem using GPU
Yelmewad, P.
;
Talawar, B.
-
2015
On the Cache Behavior of SPLASH-2 Benchmarks on ARM and ALPHA Processors in Gem5 Full System Simulator
Vikas, B.
;
Talawar, B.
-
2020
OP3DBFT: A power and performance optimal 3D BFT NoC architecture
Halavar, B.
;
Talawar, B.
-