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Browsing by Author Talawar B.

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Showing results 1 to 9 of 9

Issue Date	Title	Author(s)	Supervisor(s)
2020	An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks	Prabhu Prasad B.M.; Parane K.; Talawar B.	-
2020	ELBA-NoC: Ensemble learning-based accelerator for 2D and 3D network-on-chip architectures	Kumar A.; Talawar B.	-
2019	Floorplan Based Performance Estimation of Network-on-Chips using Regression Techniques	Kumar A.; Talawar B.	-
2021	FPGA friendly NoC simulation acceleration framework employing the hard blocks	Prasad B.M.P.; Parane K.; Talawar B.	-
2020	GPU-based Parallel Heuristics for Capacited Vehicle Routing Problem	Yelmewad P.; Talawar B.	-
2020	P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA	Parane K.; Prabhu Prasad B.M.; Talawar B.	-
2020	Parallel deterministic local search heuristic for minimum latency problem	Yelmewad P.; Talawar B.	-
2020	Power and performance analysis of 3D network-on-chip architectures	Halavar B.; Talawar B.	-
2020	PowerDPDK: Software-Based Real-Time Power Measurement for DPDK Applications	Shah M.; Yunus M.; Vachhani P.; Monis L.; Tahiliani M.P.; Talawar B.	-

Showing results 1 to 9 of 9