A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption

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DC Field	Value	Language
dc.contributor.author	Lad, K.
dc.contributor.author	Bhat, M.S.
dc.date.accessioned	2020-03-30T09:58:29Z	-
dc.date.available	2020-03-30T09:58:29Z	-
dc.date.issued	2013
dc.identifier.citation	2013 International Conference on Computer Communication and Informatics, ICCCI 2013, 2013, Vol., , pp.-	en_US
dc.identifier.uri	http://idr.nitk.ac.in/jspui/handle/123456789/7090	-
dc.description.abstract	A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. � 2013 IEEE.	en_US
dc.title	A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption	en_US
dc.type	Book chapter	en_US
Appears in Collections:	2. Conference Papers

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