Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)

Abstract

A Through Silicon Via(TSV) interconnects vertically stacked layers of circuit elements in a 3D IC. This leads to reduced distance and increased communication bandwidth between any two circuit elements located on different layers of the chip compared to 2D NoCs. TSVs have different physical characteristics and associated latency and power consumption compared to horizontal chip interconnects. The need of the hour is to accurately estimate the power consumption and latency of TSVs separately from horizontal interconnects through simulation. Accurate power and latency models of TSVs enable architects and researchers to arrive at the optimal design space by performing quick trade-off studies. We propose an extension to the BookSim simulator that considers TSVs as a separate type of on-chip interconnect. The associated latency and dynamic power consumption is calculated based on delay and power models involving various physical parameters of the TSV. Upon applying these models in a 3D 4times 4times 4 mesh topology simulation, it is observed that the total average link power consumed is lower than a 2D mesh by 13% when the vertical links(containing TSVs) are treated separately from the horizontal links. Additionally, the average network latency in the 3D mesh topology is roughly 60-82% lower than the 2D case. � 2018 IEEE.