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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Prajwal, M.V. | |
| dc.contributor.author | Srinivas, B.S. | |
| dc.contributor.author | Shodhan, S. | |
| dc.contributor.author | Reddy, M.K.J. | |
| dc.contributor.author | Laxminidhi, T. | |
| dc.date.accessioned | 2020-03-30T09:59:15Z | - |
| dc.date.available | 2020-03-30T09:59:15Z | - |
| dc.date.issued | 2016 | |
| dc.identifier.citation | Proceedings of the IEEE International Conference on VLSI Design, 2016, Vol.2016-March, , pp.146-150 | en_US |
| dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/7492 | - |
| dc.description.abstract | This paper proposes a scheme to enhance the output resistance of a differential amplifier. A gyrator based loop is used to offer a negative resistance to cancel the output resistance of the differential amplifier. The proposed scheme can give an enhancement of about three folds (in dB) in the DC gain of the basic differential Tran conductor, without loss in linearity. The concept has been validated using a Tran conductor designed in UMC 180 nm CMOS process. The results show an enhancement of 72 dB over 22 dB gain of the basic Tran conductor. A two stage OTA designed using this scheme is found to offer least sensitivity of gain boost over output voltage swing across process corners, at nominal voltage and temperature, when compared to other methods found in literature. � 2016 IEEE. | en_US |
| dc.title | A Gyrator Based Output Resistance Enhancement Scheme for a Differential Amplifier | en_US |
| dc.type | Book chapter | en_US |
| Appears in Collections: | 2. Conference Papers | |
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