Please use this identifier to cite or link to this item:
http://idr.nitk.ac.in/jspui/handle/123456789/8269
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sharma, B.S. | |
dc.contributor.author | Bhat, M.S. | |
dc.date.accessioned | 2020-03-30T10:18:18Z | - |
dc.date.available | 2020-03-30T10:18:18Z | - |
dc.date.issued | 2018 | |
dc.identifier.citation | Proceedings of 2017 International Conference on Innovations in Information, Embedded and Communication Systems, ICIIECS 2017, 2018, Vol.2018-January, , pp.1-5 | en_US |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/8269 | - |
dc.description.abstract | Inclusion of the III-V semiconductors in Field Effect Transistor technology is frequent, now days. In this paper, a tri-gate FinFET using InGaAs is proposed. Current carrying capability of the FinFET is usually large, since tri-gate structure, hence an appropriate doping in the channel would improve the ON and OFF characteristics of the device. To get an excellent ION/Ioff, doping concentration in the channel and source/drain region is varied according to material requirements. Channel length Lg of the proposed device is 20 nm. With high-K dielectric H fO2 as oxide, metal gate-oxide stack in the FinFET is designed and simulations are performed. Simulation of FinFET with gate-oxide thickness tox = 1 nm and a channel width Wc = 10nm, exhibits Ion/Ioff = 10.801 � 103, subthreshold slope SS ? 62 mV/decade and drain-induced-barrier-lowering DIBL = 83.3 mV/V. � 2017 IEEE. | en_US |
dc.title | Improved tri-gate FinFET transistor with InGaAs | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.