Please use this identifier to cite or link to this item: http://idr.nitk.ac.in/jspui/handle/123456789/8565
Title: NoC based distributed partitionable memory system for a coarse grain reconfigurable architecture
Authors: Tajammul, M.A.
Shami, M.A.
Hemani, A.
Moorthi, S.
Issue Date: 2011
Citation: Proceedings of the IEEE International Conference on VLSI Design, 2011, Vol., , pp.232-237
Abstract: This paper presents a Network-on-Chip based distributed partitionable memory system for a Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to extend the Register File (RFile) interface with additional data handling capability. The proposed interconnect which enables the interaction between existing partition of computation fabric and the distributed memory system is programmable and partitionable. The system can modify its memory to computation element ratio at runtime. The interconnect can provide multiple interfaces that can support upto 8 GB/s per interface. � 2011 IEEE.
URI: http://idr.nitk.ac.in/jspui/handle/123456789/8565
Appears in Collections:2. Conference Papers

Files in This Item:
File Description SizeFormat 
8565.pdf566.33 kBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.