A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL

Please use this identifier to cite or link to this item: http://idr.nitk.ac.in/jspui/handle/123456789/9584

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DC Field	Value	Language
dc.contributor.author	Lad, Kirankumar, H.	-
dc.contributor.author	Rekha, S.	-
dc.contributor.author	Laxminidhi, T.	-
dc.date.accessioned	2020-03-31T06:51:11Z	-
dc.date.available	2020-03-31T06:51:11Z	-
dc.date.issued	2020	-
dc.identifier.citation	Circuits, Systems, and Signal Processing, 2020, Vol.39,8 , pp.3819–3832	en_US
dc.identifier.uri	10.1007/s00034-020-01366-1	-
dc.identifier.uri	http://idr.nitk.ac.in/jspui/handle/123456789/9584	-
dc.description.abstract	This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (Fmax) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 ? W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 ? m 2. 2020, Springer Science+Business Media, LLC, part of Springer Nature.	en_US
dc.title	A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL	en_US
dc.type	Article	en_US
Appears in Collections:	1. Journal Articles

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